1. Field of Invention
The present invention relates to the etching of a barrier layer. More particularly, the invention relates to the etching of an integrated circuit (IC) structure having a barrier material such as silicon nitride (SiN) and silicon carbide (SiC).
2. Description of Related Art
Semiconductor devices are typically formed on a semiconductor substrate and often include multiple levels of patterned and interconnected layers. For example, many semiconductor devices have multiple layers of conductive lines (e.g., interconnects). Conductive lines or other conducting structures, such as gate electrodes, are typically separated by dielectric material (i.e., insulating material) and may be coupled together, as needed, by vias through the dielectric material.
During the semiconductor integrated circuit (IC) fabrication process, devices such as component transistors are formed on a semiconductor wafer substrate. Various materials are then deposited on different layers in order to build a desired IC. Typically, conductive layers may include patterned metallization lines, polysilicon transistor gates and the like which are insulated from one another with dielectric materials such as low-k dielectric materials.
Low-k materials are incorporated into IC fabrication using a copper dual damascene process. A dual damascene structure employs an etching process that creates trenches for lines and holes for vias. The vias and trenches are then metallized to form the interconnect wiring. The two well-known dual damascene schemes are referred to as a via first sequence and a trench first sequence.
During the dual damascene process, one or more barrier layers are typically used to protect material adjacent the copper (Cu) interconnects in the semiconductor devices from being poisoned by copper (Cu) atoms diffusing from the copper (Cu) interconnect into the adjacent material. For example, the barrier layer(s) may protect adjacent silicon-containing structures from being poisoned by copper (Cu) atoms diffusing from the copper (Cu) interconnect into the adjacent silicon-containing structures.
A typical barrier layer is also referred to as a “diffusion barrier layer” or as an “etch stop layer”. One commonly used barrier layer is silicon nitride (Si3N4) or SiN for short. Another commonly used barrier layer is amorphous silicon carbide or some combination of SiCXNYHZOW.
In prior art methods, oxygen (O2) or O2 containing gas mixtures have been used to etch silicon nitride. However, the use of O2 and/or O2 containing gas mixtures has resulted in damaging the copper interconnects. By way of example, the O2 containing gas mixtures may include a hydro-fluoro-carbon gas such as CH2F2, and/or a fluoro-carbon gas such as CF4. Thus, the selectivity ratio between a SiN layer to a silicon oxide containing dielectric layer is too low. Furthermore O2 free gases, such as CH3F, N2, and H2, generate undesirable polymers that are deposited on the IC structure. Therefore, each of the gas combinations, i.e, O2 containing gas mixtures and O2 free gases, has an associated limitation when etching a barrier layer.